1. Field of the Invention
The present invention relates to a plasma display apparatus, and more particularly, to a plasma display apparatus which can lower a discharge voltage by decreasing parasitic capacitance of a panel, thereby reducing power consumption.
2. Description of the Background Art
A cathode ray tube (CRT) or a Braun tube which has been mainly used up to now has a defect of a large weight and a large volume. Therefore, various kinds of flat panel displays (FPD) which can overcome the limit of such a cathode ray tube have been developed.
As a flat panel display, there are a liquid crystal display (LCD), a plasma display panel (hereinafter, referred to as “PDP”), a field emission display (FED), an electro luminescence (EL), etc.
Among such a flat panel display, a PDP which can easily manufacture a large size of panel has been in the spotlight. A PDP displays an image and moving images including a character or a graphic by allowing a phosphor to emit light by ultraviolet rays of 147 nm generating upon discharging of He+Xe, Ne+Xe, and He+Ne+Xe gas. Such a PDP displays an image by adjusting a discharge period of each pixel depending on video data and provides a picture quality which is greatly improved thanks to the recent technical development.
Specifically, a three-electrode AC surface-discharge PDP lowers a voltage required for discharge by accumulating wall charges using a dielectric layer upon discharging and protects electrodes from sputtering of plasma, so that it has an advantage of a low voltage drive and a long lifetime.
FIG. 1 is a perspective view illustrating a discharge cell of a three-electrode AC surface-discharge PDP in the related art.
Referring to FIG. 1, the discharge cell of the three-electrode AC surface-discharge PDP includes a scan electrode (Y) and a sustain electrode (Z) which are formed on an upper substrate 10 and an address electrode (X) which is formed on a lower substrate 18. Each of the scan electrode (Y) and the sustain electrode (Z) includes transparent electrodes (12Y, 12Z) and metal bus electrodes (13Y, 13Z) which have a line width smaller than that of the transparent electrode (12Y, 12Z) and which are formed in one edge of the transparent electrode.
The transparent electrodes (12Y, 12Z) are generally made of a metal such as an indium tin oxide (ITO), an indium zinc oxide (IZO), and an indium tin zinc oxide (ITZO) and formed on the upper substrate 10. The metal bus electrodes (13Y, 13Z) are generally made of a metal such as chrome (Cr) and formed on the transparent electrodes (12Y, 12Z) to reduce a drop in voltage by the transparent electrodes (12Y, 12Z) having high resistance. An upper dielectric layer 14 and a protective film 16 are stacked in the upper substrate 10 in which the scan electrode (Y) and the sustain electrode (Z) are formed in parallel.
The protective film 16 prevents damage of the upper dielectric layer 14 by sputtering generated upon discharging plasma and increases emission efficiency of a secondary electron. A magnesium oxide (MgO) is generally used as the protective film 16.
A lower dielectric layer 22 and a barrier rib 24 are formed on a lower substrate 18 in which the address electrode (X) is formed and a phosphorous layer 26 is coated on the surface of the lower dielectric layer 22 and the barrier rib 24. The address electrode (X) is formed in a direction to intersect the scan electrode (Y) and the sustain electrode (Z).
Wall charges formed due to discharge are stacked in the upper dielectric layer 14 and the lower dielectric layer 22. The dielectric layers 14 and 22 and the protective film 16 can lower a discharge voltage applied from the outside.
The barrier rib 24 and the upper and lower substrates 10 and 18 form a discharge space. The barrier rib 24 is formed in parallel to the address electrode 20 and prevents ultraviolet rays and visible rays generated by gas discharge from being leaked to an adjacent discharge cell. An inert gas such as He, Ne, Ar, Xe, and Kr for gas discharge, a discharge gas (or mixed gas) with which these gases are combined, or an excimer gas which can generate ultraviolet rays due to discharge are filled in a discharge space formed between the upper and lower substrates 10 and 18 and the barrier rib 24.
The phosphorous layer 26 is excited by ultraviolet rays generated upon discharging plasma and generates any one visible ray of red color (R), green color (G) or blue color (B).
FIG. 2A shows a barrier rib and an upper substrate in the related art and FIG. 2B shows parasitic capacitance formed in the barrier rib in the related art.
As shown in FIG. 2A, in a PDP in the related art, the scan electrode (Y) and the sustain electrode (Z) are formed in the upper substrate 10 and the dielectric layer 14 is formed to cover the scan electrode (Y) and the sustain electrode (Z) and the upper substrate 10. As the barrier rib 24 is positioned in a right lower portion of the protective film 16 after the protective film 16 is coated on the dielectric layer 14, the discharge space is partitioned.
As shown in FIG. 2B, the scan electrode (Y) and the sustain electrode (Z) formed in a direction intersecting the barrier rib 24 are positioned in this portion and charges are charged by a driving signal applied to the scan electrode (Y) and the sustain electrode (Z). That is, parasitic capacitance is formed by elements having a dielectric constant around the electrodes (Y, Z).
The dielectric layer 14 and the protective film 16 which are formed between the barrier rib 24 and the upper substrate 10 and the upper substrate 10 form parasitic capacitance of a non-discharge area. This is because dielectric constants of glass, the dielectric layer 14, and the protective film 16 which are used as a material of the upper substrate 10 are different from each other. Among them, because parasitic capacitance (Cs) between electrodes generated in the protective film 16 is much smaller than parasitic capacitances (C, Cg) generated in the upper substrate 10 or the dielectric layer 14, it does not greatly matter.
In addition, the parasitic capacitance (Cg) between electrodes generated in the upper substrate 10 is greatly improved by recently adopting a glass substrate having a low dielectric constant.
Even in the dielectric layer 14, the parasitic capacitance (C) is generated between the electrodes (Y, Z). Specifically, a portion shown in FIG. 2B is an area which partitions a discharge space as the barrier rib 24 and the upper substrate 10 come in contact with each other and is a non-discharge area which discharge is not generated. The dielectric layer 14 in the discharge area serves as lowering a discharge voltage by charging wall charges upon discharging, but there is a problem that the dielectric layer 14 in the non-discharge area increases a magnitude of a voltage required for discharge by the parasitic capacitance (C) that is not concerned in the discharge. In addition, if a magnitude of a voltage required upon discharging increases, there is a problem that consumption power increases in an entire plasma display panel.